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JEDEC JESD8-6 PDF
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ADDENDUM No. 6 to JESD8 – HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
| Published by | Publication Date | Number of Pages |
| JEDEC | 08/01/1995 | 20 |
JEDEC JESD8-6 – ADDENDUM No. 6 to JESD8 – HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
This standard is a 1.5 volt high performance CMOS-based interface document suitable for high I/O count CMOS and BiCMOS devices operating at frequencies in excess of 200 Mhz.
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