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JEDEC JESD203 PDF
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STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES
| Published by | Publication Date | Number of Pages |
| JEDEC | 11/01/2005 | 9 |
JEDEC JESD203 – STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES
This standard defines ac test loads for dual-supply level translation devices. Uniform test loads enable easy comparison of electrical parameters of dual-supply level translation devices across functions, logic families and IC suppliers. This standard is only intended to apply to devices released subsequent to the publication of this document.
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