IPC J-STD-012 PDF

Implementation of Flip Chip and Chip Scale Technology

IPC J-STD-012 – Implementation of Flip Chip and Chip Scale Technology

This informative document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data. Chip packaging variations include flip chip, HDI, micro BGA, micro SMT and SLICC. Also provides general information on implementing flip chip and chip scale technologies for creating multichip modules, I/C cards, memory cards and very dense surface mount assemblies. Co- developed by IPC, EIA, MCNC and Sematech.