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IEC 63011-1 Ed. 1.0 b PDF
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Integrated circuits – Three dimensional integrated circuits – Part 1: Terminology
| Published by | Publication Date | Number of Pages |
| IEC | 11/28/2018 | 24 |
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IEC 63011-1 Ed. 1.0 b – Integrated circuits – Three dimensional integrated circuits – Part 1: Terminology
IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.
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