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IEC 62050 Ed. 1.0 en PDF
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VHDL Register Transfer Level (RTL) synthesis
| Published by | Publication Date | Number of Pages |
| IEC | 07/19/2005 | 121 |
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IEC 62050 Ed. 1.0 en – VHDL Register Transfer Level (RTL) synthesis
Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.
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