ASTM F1771 PDF

Standard Test Method for Evaluating Gate Oxide Integrity by Voltage Ramp Technique (Withdrawn 2003)

ASTM F1771 – Standard Test Method for Evaluating Gate Oxide Integrity by Voltage Ramp Technique (Withdrawn 2003)

This standard was transferred to SEMI (www.semi.org) May 2003

1.1 The techniques outlined in this standard are for the purpose of standardizing the procedure of measurement, analysis, and reporting of oxide integrity data between interested parties. This test method makes no representation regarding actual device failure rates or acceptance/rejection criteria. While some suggestions for data analysis are included in later sections of this test method, interpretation of results is beyond the scope of this standard. Any such interpretations should be agreed upon between interested parties prior to testing. For example, a variety of failure criteria are included to permit separation of so-called intrinsic and extrinsic oxide failures.

1.2 This test method covers the procedure for gaging the electrical strength of silicon dioxide thin films with thicknesses ranging from approximately 3 nm to 50 nm. In the analysis of films of 4 nm or less, the impact of direct tunneling on the current-voltage characteristics, and hence the specified failure criteria defined in 5.4, must be taken into account. Since oxide integrity strongly depends on wafer defects, contamination, cleanliness, as well as processing, the users of this test method are expected to include wafer manufacturers and device manufacturers.

1.3 This test method is not structure specific, but notes regarding options for different structures may be found in the appendix. The three most likely structures are simple planar metal-oxide semiconductor (MOS-capacitors) (fabricated or mercury probe), various isolation structures (for example, local oxidation of silicon (LOCOS)), and field effect transistors. This test method assumes that a low resistance ohmic contact is made to the backside of each wafer in each case. For a more detailed discussion of the design and evaluation of test structures for this test method, the reader is referred to the EIA/JEDEC Standard 35-1.

1.4 Failure criteria specified in this test method include both the fixed current limit (soft) and destructive (hard) types. In the past, use of a fixed current limit of 1 &microA or more virtually ensured measurement of hard failure, as the thicker, more heavily contaminated oxides of those days typically failed catastrophically as soon as measurable currents were passed. The cleaner processing of thinner oxides now means that oxides will sustain relatively large currents with little or no evidence of failure. While use of fixed current limit testing may still be of value for assessing uniformity issues, it is widely felt that failure to continue oxide breakdown testing to the point of catastrophic oxide failure may mask the presence of defect tails, which are of critical importance in assessing long-term oxide reliability. For this reason, this test method makes provision for use of fixed limit failure criteria if desired and agreed upon by the parties to the testing, but specifies that testing be continued until hard failure is sensed.

1.5 This test method specifically does not include measurement of a charge-to-breakdown (Q_bd) parameter. Industry experience with this parameter measured in a ramp-to-failure test such as this indicates that Q_bd values so obtained may be unreliable indicators of oxide quality. This is because a large fraction of the value determined is collected in the last steps of the test, and the result is subject to large deviations. Q_bd should be measured in a constant current or bounded current ramp test.

1.6 This test method is applicable to both n-type and p-type wafers, polished or having an epitaxial layer. In wafers with epitaxial layers, the conductivity type of the layer should be the same as that of the bulk wafer. While not excluding depletion polarity, it is preferred that measurement polarity should be in accumulation to avoid the complication of a voltage drop across the depletion layer.

1.7 While this test method is primarily intended for use in characterizing the SiO₂-silicon systems as stated above, it may be applied in general terms to the measurement of other metal-insulator-semiconductor structures if appropriate consideration of the characteristics of the other materials is made.

1.8 Measurement conditions specified in this test method are conservative, intended for thorough analysis of high quality oxide-silicon systems, and to provide a regime in which new users may safely begin testing without encountering undue experimental artifacts. It is recognized that some experienced users may be working in applications where less precise data is required and a more rapid test is desirable. An example of this situation is the evaluation of silicon wafer quality, where a staircase voltage step providing 0.5 MV/cm oxide field strength resolution and a voltage step duration of 0.2 s has been used. Such test conditions may be specified when agreed upon as adequate by all participants to the testing. Because the dependence of measured parameters upon test conditions may increase as these conditions depart from those specified in this test method, it is important that all parties to these tests use the same set of test conditions, so that their results will be comparable.

1.9 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.